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Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Features
* 2 LVCMOS / LVTTL outputs * 2 differential CLKx, nCLKx input pairs * CLK, nCLK pairs can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 350MHz (typical) * Output skew: 60ps (maximum) * Part-to-part skew: 500ps (maximum) * Small 8 lead SOIC package saves board space * 3.3V operating supply * -40C to 85C ambient operating temperature * Pin-to-pin compatible with MC100EPT23
GENERAL DESCRIPTION
The ICS83023I is a dual, 1-to-1 Differential-toLVCMOS Translator/Fanout Buffer and a member HiPerClockSTM of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The differential inputs can accept most differential signal types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and translate into two single-ended LVCMOS outputs. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space.
,&6
BLOCK DIAGRAM
CLK0 nCLK0 CLK1 nCLK1 Q0
PIN ASSIGNMENT
CLK0 nCLK0 nCLK1 CLK1 1 2 3 4 8 7 6 5 VDD Q0 Q1 GND
Q1
ICS83023I
8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View
83023AMI
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Type Input Input Input Input Power Output Output Power Pullup Pullup Description Inver ting differential clock input. Inver ting differential clock input. Power supply ground. Single clock output. LVCMOS / LVTTL interface levels. Single clock output. LVCMOS / LVTTL interface levels. Positive supply pin.
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8 Name CLK0 nCLK0 nCLK1 CLK1 GND Q1 Q0 VDD Pulldown Non-inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN CPD RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor Input Pulldown Resistor Output Impedance Test Conditions Minimum Typical Maximum 4 VDD = 3.6V 23 51 51 7 Units pF pF K K
83023AMI
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
4.6V -0.5V to VDD+ 0.5V -0.5V to VDD + 0.5V 112.7C/W (0 lfpm) -65C to 150C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol VDD IDD Parameter Positive Supply Voltage Positive Supply Current Test Conditions Minimum 3.0 Typical 3.3 Maximum 3.6 20 Units V mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol VOH VOL Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Test Conditions Minimum 2.6 0.5 Typical Maximum Units V V
NOTE 1: Outputs terminated with 50 to VDD/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK0, nCLK1 CLK0, CLK1 nCLK0, nCLK1 CLK0, CLK1 Test Conditions VIN = VDD = 3.6V VIN = VDD = 3.6V VIN = 0V, VDD = 3.6V VIN = 0V, VDD = 3.6V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single-ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH.
83023AMI
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Test Conditions Minimum 1.8 Typical 350 2.1 2.4 60 500 0.8V to 2V 0.8V to 2V f 166MHz 100 100 45 250 250 50 400 400 55 57 Maximum Units MHz ns ps ps ps ps % %
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V0.3V, TA = -40C TO 85C
Symbol Parameter fMAX tPD Maximum Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time Output Duty Cycle
tsk(o) tsk(pp)
tR tF odc
f > 166MHz 43 50 All parameters measured at fMAX unless noted otherwise. See Parameter Measurement Information. NOTE 1: Measured from the differential input crossing point to VDD/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2. Input clocks are phase aligned. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83023AMI
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V0.15V
V DD
SCOPE
LVCMOS
GND
Qx
-1.65V 0.15V
3.3V OUTPUT LOAD TEST CIRCUIT
VDD
nCLK0, nCLK1 V CLK0, CLK1
PP
Cross Points
V
CMR
GND
DIFFERENTIAL INPUT LEVEL
83023AMI
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
V
DD
Qx
2
V
Qy
DD
2 tsk(o)
OUTPUT SKEW
PART 1 Qx
V
DD
2
PART 2 Qy
V
DD
2 tsk(pp)
PART-TO-PART SKEW
2V
2V
0.8V Clock Outputs t
R
0.8V t
AND
F
OUTPUT RISE
FALL TIME
83023AMI
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
nCLK0, nCLK1 CLK0, CLK1
V
DD
Q0, Q1
2 t
PD
PROPAGATION DELAY
V Q0, Q1
DD
V
DD
V
DD
2 t
PW
2
2
t t odc = t
PW
PERIOD
PERIOD
tPW & tPERIOD
83023AMI
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 1 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
83023AMI
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER RELIABILITY INFORMATION
TABLE 5. JAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W
200
128.5C/W 103.3C/W
500
115.5C/W 97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83023I is: 416
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
PACKAGE OUTLINE - SUFFIX M
TABLE 6. PACKAGE DIMENSIONS
SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM
Reference Document: JEDEC Publication 95, MS-012
83023AMI
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
Marking 83023AMI 83023AMI Package 8 lead SOIC 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature -40C to 85C -40C to 85C
TABLE 7. ORDERING INFORMATION
Part/Order Number ICS83023AMI ICS83023AMIT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industiral applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83023AMI
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REV. A SEPTEMBER 9, 2002
Integrated Circuit Systems, Inc.
ICS83023I
DUAL, 1-TO-1 DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER
REVISION HISTORY SHEET Description of Change Ordering Information Table - corrected Par t/Order Number for Tape & Reel to read ICS83023AMIT from ICS83023AMI. Date 09/09/02
Rev A
Table 7
Page 11
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REV. A SEPTEMBER 9, 2002

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